The controller sits waiting. It receives a command, checks it for validity, decides what to do with it (move it to the motion control stack and work on it, or return a response to a query) and indicates itâs ready for the next command
Lighburn is monitoring the serial port and sends the commands when told to by the UART
The controller, once the buffer is full, will indicate this, until it has capacity to receive more data.
If the motion is small, the motion can be processed much faster than the serial connection can be filled, resulting in the controller waiting for the next command from LightBurn.
itâs all controlled by serial UART at a level below that of both the controller microcode and LightBurn.
The receiver tests the state of the incoming signal on each clock pulse, looking for the beginning of the start bit. If the apparent start bit lasts at least one-half of the bit time, it is valid and signals the start of a new character. If not, it is considered a spurious pulse and is ignored. After waiting a further bit time, the state of the line is again sampled and the resulting level clocked into a shift register. After the required number of bit periods for the character length (5 to 8 bits, typically) have elapsed, the contents of the shift register are made available (in parallel fashion) to the receiving system. The UART will set a flag indicating new data is available, and may also generate a processor interrupt to request that the host processor transfers the received data.
Communicating UARTs have no shared timing system apart from the communication signal. Typically, UARTs resynchronize their internal clocks on each change of the data line that is not considered a spurious pulse. Obtaining timing information in this manner, they reliably receive when the transmitter is sending at a slightly different speed than it should. Simplistic UARTs do not do this; instead they resynchronize on the falling edge of the start bit only, and then read the center of each expected data bit, and this system works if the broadcast data rate is accurate enough to allow the stop bits to be sampled reliably.
It is a standard feature for a UART to store the most recent character while receiving the next. This âdouble bufferingâ gives a receiving computer an entire character transmission time to fetch a received character. Many UARTs have a small first-in, first-out (FIFO) buffer memory between the receiver shift register and the host system interface. This allows the host processor even more time to handle an interrupt from the UART and prevents loss of received data at high rates.
